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M34D64 M34D32
64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory
PRELIMINARY DATA
s s
Compatible with I2C Extended Addressing Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage: - 4.5V to 5.5V for M34Dxx - 2.5V to 5.5V for M34Dxx-W - 1.8V to 3.6V for M34Dxx-R
s
8 1
PSDIP8 (BN) 0.25 mm frame
s
Hardware Write Control of the top quarter of memory BYTE and PAGE WRITE (up to 32 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
s s s s s s s
8 1
SO8 (MN) 150 mil width
DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are fabricated with STMicroelectronics' High Endurance, CMOS technology. This guarantees an endurance typically well above one million Erase/Write cycles, with a data retention of 40 years. The memories are organized as 8192x8 bits (M34D64) and 4096x8 bits (M34D32), and operate down to
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
E0, E1, E2 SDA Chip Enable Inputs Serial Data/Address Input/ Output Serial Clock Write Control Supply Voltage Ground
3 E0-E2 SCL WC M34D64 M34D32 SDA
SCL WC VCC VSS
VSS
AI02850
May 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/15
M34D64, M34D32
Figure 2A. DIP Connections 2.5 V (for the -W version of each device), and down to 1.8 V (for the -R version of each device). The M34D64 and M34D32 are available in Plastic Dual-in-Line and Plastic Small Outline packages. These memory devices are compatible with the I2C extended memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the V CC voltage has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when V CC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and
M34D64 M34D32 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI02851
VCC WC SCL SDA
Figure 2B. SO Connections
M34D64 M34D32 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI02852
VCC WC SCL SDA
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 PSDIP8: 10 sec SO8: 40 sec Value -40 to 125 -65 to 150 260 215 -0.6 to 6.5 -0.3 to 6.5 4000 Unit C C C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 ) 3. EIAJ IC-121 (Condition C) (200 pF, 0 )
2/15
M34D64, M34D32
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
valid VCC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the master has a push-pull (rather than open drain) output. Serial Data (SDA) The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E2, E1, E0) These chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to V CC or VSS to establish the device select code. Write Control (WC) The hardware Write Control pin (WC) is useful for protecting the top quarter of the memory (as shown in Figure 4) from inadvertent erase or write. The Write Control signal is used to enable
(WC=VIL) or disable (WC=VIH) write instructions to the top quarter of the memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed. DEVICE OPERATION The memory device supports the I2C protocol. This is summarized in Figure 5, and is compared with other serial bus protocols in Application Note AN1001. Any device that sends data on to the bus is defined to be a transmitter, and any device that Figure 4. Memory Map of Write Control Areas
1FFh Write Controlled Area 180h
FFh C0h Write Controlled Area
100h
80h
80h
40h
00h M34D32
000h M34D64
AI03114
3/15
M34D64, M34D32
Figure 5. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communication. Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given. Stop Condition STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high
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M34D64, M34D32
Table 3. Device Select Code 1
Device Type Identifier b7 Device Select Code 1 b6 0 b5 1 b4 0 b3 E2 Chip Enable b2 E1 b1 E0 RW b0 RW
Note: 1. The most significant bit, b7, is sent first.
transition, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b. If all three chip enable inputs are connected, up to eight memory devices can be connected on a single I 2C bus. Each one is given a unique 3-bit code on its Chip Enable inputs. When the Device Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the same as the pattern applied to its Chip Enable pins. The 8th bit is the RW bit. This is set to `1' for read and `0' for write operations. If a match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9 th bit time. If the memory does not match the Device Select Code, it deselects itself from the bus, and goes into stand-by mode. There are two modes both for read and write. These are summarized in Table 6 and described
Table 4. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 to b13 are Don't Care on the M34D64 series. b15 to b12 are Don't Care on the M34D32 series.
Table 5. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
later. A communication between the master and the slave is ended with a STOP condition. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least significant Byte (Table 5). Bits b15 to b0 form the address of the byte in memory. Bits b15 to b13 are treated as a Don't Care bit on the M34D64 memory. Bits b15 to b12 are treated as Don't Care bits on the M34D32 memory. Write Operations Following a START condition the master sends a Device Select Code with the RW bit set to '0', as shown in Table 6. The memory acknowledges this, and waits for two address bytes. The memory responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with WC=1 (during a period of time from the START condition until the end of the two address bytes) will not modify the contents of the top quarter of the memory.
Table 6. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1'
X X VIL VIL 1 1
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = `0'
32
START, Device Select, RW = `0'
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M34D64, M34D32
Figure 6. Write Mode Sequences
ACK BYTE WRITE START DEV SEL R/W
ACK
ACK DATA IN
ACK
BYTE ADDR
BYTE ADDR
ACK PAGE WRITE START DEV SEL R/W
ACK
ACK DATA IN 1
ACK DATA IN 2
BYTE ADDR
BYTE ADDR
ACK PAGE WRITE (cont'd) DATA IN N
ACK
STOP
STOP
AI02853
Byte Write In the Byte Write mode, after the Device Select Code and the address bytes, the master sends one data byte. If the addressed location is write protected by the WC pin, the location is not modified. The master terminates the transfer by generating a STOP condition. Page Write The Page Write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same "row" in the memory: that is the most significant memory address bits (b12-b5 for the M34D64 and b11-b5 for the M34D32) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. Data starts to become overwritten (in a way not formally specified in this data sheet). The master sends from one up to 32 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the
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contents of the addressed memory location are not modified. After each byte is transferred, the internal byte address counter (the 5 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. When the master generates a STOP condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. A STOP condition at any other time does not trigger the internal write cycle. During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests. Minimizing System Delays by Polling On ACK During the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum write time (tw) is shown in Table 9, but the typical time is shorter. To make use of this,
M34D64, M34D32
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by M24xxx
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI01847
an Ack polling sequence can be used by the master. The sequence, as shown in Figure 7, is: - Initial condition: a Write is in progress. - Step 1: the master issues a START condition followed by a Device Select Code (the first byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it responds with an Ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1). Read Operations Read operations are performed independently of the state of the WC pin.
Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 8. Then, without sending a STOP condition, the master sends another START condition, and repeats the Device Select Code, with the RW bit set to `1'. The memory acknowledges this, and outputs the contents of the addressed byte. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to 1. The memory acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The master terminates the transfer with a STOP condition, as
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M34D64, M34D32
Figure 8. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
NO ACK DATA OUT STOP ACK
BYTE ADDR
BYTE ADDR
R/W
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
NO ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL *
ACK
ACK DEV SEL * START
ACK
BYTE ADDR R/W
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
AI01105C
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
st
th
shown in Figure 8, without acknowledging the byte output. Sequential Read This mode can be initiated with either a Current Address Read or a Random Address Read. The master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a STOP condition. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output.
After the last memory address, the address counter `rolls-over' and the memory continues to output data from the start of the memory block. Acknowledge in Read Mode In all read modes, the memory waits, after each byte read, for an acknowledgment during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its standby state.
8/15
M34D64, M34D32
Table 7. DC Characteristics (TA = 0 to 70 C or -40 to 85 C; (TA = 0 to 70 C or -20 to 85 C;
Symbol ILI ILO Parameter Input Leakage Current (SCL, SDA) Output Leakage Current
VCC = 4.5 to 5.5 V or 2.5 to 5.5 V) VCC = 1.8 to 3.6 V 1)
Test Condition 0 V VIN VCC 0 V VOUT VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) Min. Max. 2 2 2 1 0.81 10 2 11 -0.3 0.7VCC -0.3 0.7VCC IOL = 3 mA, VCC = 5 V 0.3 VCC VCC+1 0.5 VCC+1 0.4 0.4 0.21 Unit A A mA mA mA A A A V V V V V V V
ICC
Supply Current
-W series: -R series:
VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VCC =1.8V, fc=100kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V VIN = VSS or VCC , VCC = 2.5 V VIN = VSS or VCC , VCC = 1.8 V
ICC1 ICC2 ICC3 VIL VIH VILW VIHW
Supply Current (Stand-by) Supply Current (Stand-by) Supply Current (Stand-by) Input Low Voltage (E0-E2, SCL, SDA) Input High Voltage (E0-E2, SCL, SDA) Input Low Voltage (WC) Input High Voltage (WC)
VOL
Output Low Voltage
-W series: -R series:
IOL = 2.1 mA, VCC = 2.5 V IOL = 0.15 mA, VCC = 1.8 V
Note: 1. This is preliminary data.
Table 8. Input Parameters1 (TA = 25 C, f = 400 kHz)
Symbol CIN CIN ZWCL ZWCH tNS Parameter Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Pulse width ignored (Input Filter on SCL and SDA) VIN < VILW VIN > VIHW Single glitch 50 500 50 Test Condition Min. Max. 8 6 300 Unit pF pF k k ns
Note: 1. Sampled only, not 100% tested.
9/15
M34D64, M34D32
Table 9. AC Characteristics
M34D64 / M34D32 Symbol Alt. Parameter VCC=4.5 to 5.5 V VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V TA=0 to 70C or TA=0 to 70C or TA=0 to 70C or Unit -40 to 85C -40 to 85C -20 to 85C4 Min tCH1CH2 tCL1CL2 tDH1DH2
2
Max 300 300
Min
Max 300 300
Min
Max 1000 300 ns ns ns ns ns ns ns s s ns ns s 3500 ns ns 100 10 kHz ms
tR tF tR tF tSU:STA tHIGH tHD:STA
Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) 20 20 600 600 600 0 1.3 100 600 1.3 200 200
300 300
20 20 600 600 600 0 1.3 100 600 1.3
300 300
20 20 4700 4000 4000 0 4.7 250 4000 4.7
1000 300
tDL1DL2 2 tCHDX
1
tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV 3 tCLQX fC tW
Note: 1. 2. 3. 4.
tHD:DAT Clock Low to Input Transition tLOW tSU:DAT Clock Pulse Width Low Input Transition to Clock Transition
tSU:STO Clock High to Input High (STOP) tBUF tAA tDH fSCL tWR Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time After Clock Low Clock Frequency Write Time
900
200 200
900
200 200
400 10
400 10
For a reSTART condition, or following a write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. This is preliminary data.
Table 10. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Figure 9. AC Testing Input Output Waveforms
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
10/15
M34D64, M34D32
Figure 10. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE STOP & BUS FREE tDHDL tDXCX tCHDH tCLCH
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795B
11/15
M34D64, M34D32
Table 11. Ordering Information Scheme
Example: M34D64 -W MN 1 T
Memory Capacity 64 32 64 Kbit (8K x 8) 32 Kbit (4K x 8) T
Option Tape and Reel Packing
Operating Voltage blank 4.5 V to 5.5 V W R2 2.5 V to 5.5 V 1.8 V to 3.6 V
Package BN MN PSDIP8 (0.25 mm frame) SO8 (150 mil width) 11 6 5
Note: 1. Temperature range available only on request. 2. The -R version (V CC range 1.8 V to 3.6 V) only available in temperature ranges 5 or 1.
Temperature Range 0 C to 70 C -40 C to 85 C -20 C to 85 C
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all 1s (FFh).
The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
12/15
M34D64, M34D32
Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Symb. Typ. A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min. 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max. 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ. Min. 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max. 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150 inches
Figure 11. PSDIP8 (BN)
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Note: 1. Drawing is not to scale.
13/15
M34D64, M34D32
Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
Figure 12. SO8 narrow (MN)
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: 1. Drawing is not to scale.
14/15
M34D64, M34D32
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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